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19-3243; Rev 0; 4/04
KIT ATION EVALU E AILABL AV
Step-Up/Step-Down Li+ Battery Charger
Features
Patented Step-Up/Step-Down Control Scheme* 0.5% Charge-Voltage Accuracy 9% Charge-Current Accuracy 8% Input Current-Limit Accuracy Programmable Maximum Battery Charge Current Analog Inputs Control Charge Current, Charge Voltage, and Input Current Limit Analog Output Indicates Adapter Current Input Voltage from 8V to 28V Battery Voltage from 0 to 17.6V Charges Li+ or NiCd/NiMH Batteries Tiny 32-Pin Thin QFN (5mm x 5mm) Package
General Description
The MAX1870A step-up/step-down multichemistry battery charger charges with battery voltages above and below the adapter voltage. This highly integrated charger requires a minimum number of external components. The MAX1870A uses a proprietary step-up/stepdown control scheme that provides efficient charging. Analog inputs control charge current and voltage, and can be programmed by the host or hardwired. The MAX1870A accurately charges two to four lithiumion (Li+) series cells at greater than 4A. A programmable input current limit is included, which avoids overloading the AC adapter when supplying the load and the battery charger simultaneously. This reduces the maximum adapter current, which reduces cost. The MAX1870A provides analog outputs to monitor the current drawn from the AC adapter and charge current. A digital output indicates the presence of an AC adapter. When the adapter is removed, the MAX1870A consumes less than 1A from the battery. The MAX1870A is available in a 32-pin thin QFN (5mm x 5mm) package and is specified over the -40C to +85C extended temperature range. The MAX1870A evaluation kit (MAX1870AEVKIT) is available to help reduce design time.
MAX1870A
Ordering Information
PART MAX1870AETJ TEMP RANGE -40C to +85C PIN-PACKAGE 32 Thin QFN
Typical Operating Circuit
FROM WALL ADAPTER SYSTEM LOAD
Applications
Notebook and Subnotebook Computers Hand-Held Terminals
CSSS DCIN VHP
CSSP CSSN
VHN REF CLS
MAX1870A
DHI
P
CELLS N ASNS IINP DBST CSIP CSIN REFIN SHDN ICTL VCTL LDO PGND DLOV GND BATT BLKP
*Protected by U.S. Patent No. 6,087,816. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Step-Up/Step-Down Li+ Battery Charger MAX1870A
ABSOLUTE MAXIMUM RATINGS
DCIN, CSSP, CSSS, CSSN, VHP, VHN, DHI to GND ......................................-0.3V to +30V VHP, DHI to VHN .....................................................-0.3V to +6V BATT, CSIP, CSIN, BLKP to GND ..........................-0.3V to +20V CSIP to CSIN, CSSP to CSSN, CSSP to CSSS, PGND to GND ..........................-0.3V to +0.3V CCI, CCS, CCV, REF, IINP to GND ..........-0.3V to (VLDO + 0.3V) DBST to GND..........................................-0.3V to (VDLOV + 0.3V) DLOV, VCTL, ICTL, REFIN, CELLS, CLS, LDO, ASNS, SHDN to GND .........................-0.3V to +6V LDO Current........................................................................50mA Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN 5mm x 5mm (derate 21mW/C above +70C) ......................................1.7W Operating Temperature Range MAX1870AETJ .................................................-40C to +85C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) ................................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CHARGE-VOLTAGE REGULATION VCTL Range VVCTL = VLDO (2 cells) VVCTL = VLDO (3 cells) VVCTL = VLDO (4 cells) Battery Regulation Voltage Accuracy VVCTL = VREFIN (2 cells) VVCTL = VREFIN (3 cells) VVCTL = VREFIN (4 cells) VVCTL = VREFIN / 20 (2 cells) VVCTL = VREFIN / 20 (3 cells) VVCTL = VREFIN / 20 (4 cells) VCTL Default Threshold VCTL Input Bias Current VCTL rising 0 < VVCTL < VREFIN DCIN = 0, VREFIN = VVCTL = 3.6V VCTL = DCIN = 0, VREFIN = 3.6V CHARGE-CURRENT REGULATION ICTL Range VICTL = VREFIN Quick-Charge-Current Accuracy Trickle-Charge-Current Accuracy BATT/CSIP/CSIN Input Voltage Range DCIN = 0 CSIP Input Current ICTL = 0 ICTL = REFIN VICTL = VREFIN x 0.8 VICTL = VREFIN x 0.583 VICTL = VREFIN x 0.0625 0 67 54 39 3.0 0 0.1 0.1 350 73 59 43 4.5 3.6 79 64 47 6.0 19 2 2 600 A mV V mV V 0 -0.5 -0.5 -0.5 -0.8 -0.8 -0.8 -1.2 -1.2 -1.2 4.0 -1 -1 -1 4.1 3.6 +0.5 +0.5 +0.5 +0.8 +0.8 +0.8 +1.2 +1.2 +1.2 4.2 +1 +1 +1 A V % V CONDITIONS MIN TYP MAX UNITS
2
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Step-Up/Step-Down Li+ Battery Charger
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DCIN = 0 CSIN Input Current ICTL Power-Down-Mode Threshold Voltage ICTL Input Bias Current INPUT-CURRENT REGULATION Charger-Input Current-Limit Accuracy (VCSSP - VCSSN) System-Input Current-Limit Accuracy (VCSSP - VCSSS) CSSP/CSSS/CSSN Input Voltage Range CSSP Input Current CSSS/CSSN Input Current CLS Input Range CLS Input Bias Current IINP Transconductance IINP Output Current IINP Output Voltage CLS = REF VCSSP - VCSSS = 102mV, CSSN = CSSP VCSSP - VCSSN = 200mV, VIINP = 0V VCSSP - VCSSS = 200mV, VIINP = 0V VCSSP - VCSSN = 200mV, IINP float VCSSP - VCSSS = 200mV, IINP float VCSSP = VCSSN = VCSSS = VDCIN = 6V VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V VCSSP = VCSSN = VCSSS = VDCIN = 6V VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V -1 -1 VREF / 2 -1 2.5 350 350 3.5 3.5 8 DCIN falling DCIN rising 8.0V < VDCIN < 28V 0 DCIN = 0 VBATT = 2V to 19V No load 0 < ILDO < 10mA VDCIN = 8V, LDO rising 4.00 5.3 0.1 300 5.4 70 5.0 4 6.2 6.3 3.5 7.85 6 19 1 500 5.5 150 5.25 28 2.8 CSSS = CSSP CSSN = CSSP CLS = REF CLS = REF x 0.845 CLS = REF CLS = REF x 0.845 97 81 97 81 8 -1 700 105 88 105 88 113 95 113 95 28 +1 1200 +1 +1 VREF +1 3.1 mV mV V A A V A A/mV A V 0 < VICTL < VREFIN ICTL = DCIN = 0, VREFIN = 3.6V ICTL = 0 ICTL = REFIN REFIN / 100 -1 -1 CONDITIONS MIN TYP 0.1 0.1 0.1 REFIN / 55 MAX 2 2 2 REFIN / 32 +1 +1 V A A UNITS
MAX1870A
SUPPLY AND LINEAR REGULATOR DCIN Input Voltage Range DCIN Undervoltage Lockout DCIN Quiescent Current BATT Input Voltage Range BATT Input Bias Current LDO Output Voltage LDO Load Regulation LDO Undervoltage Lockout V V mA V A V mV V
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3
Step-Up/Step-Down Li+ Battery Charger MAX1870A
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER REFERENCE REF Output Voltage REF Load Regulation REF Undervoltage-Lockout Trip Point REFIN Input Range REFIN UVLO Rising REFIN UVLO Hysteresis REFIN Input Bias Current SWITCHING REGULATOR Cycle-by-Cycle Step-Up Maximum Current-Limit Sense Voltage Cycle-by-Cycle Step-Down Maximum Current-Limit Sense Voltage Step-Down On-Time Minimum Step-Down Off-Time Step-Up Off-Time Minimum Step-Up On-Time MOSFET DRIVERS VHP - VHN Output Voltage VHN Load Regulation DHI On-Resistance High DHI On-Resistance Low VHP Input Bias Current BLKP Input Bias Current DLOV Supply Current DBST On-Resistance High DBST On-Resistance Low ERROR AMPLIFIERS GMV Amplifier Loop Transconductance GMI Amplifier Loop Transconductance VCTL = REFIN, VBATT = 16.8V ICTL = REFIN, VCSIP - VCSIN = 72mV 0.05 1.8 0.1 2.4 0.20 3.0 A/mV A/mV 8V < VVHP < 28V, no load 0 < IVHN < 10mA ISOURCE = 10mA ISINK = 10mA DCIN = 0 VDCIN = 18V ICTL = 0 VICTL = VREFIN = 3.3V DBST low ISOURCE = 10mA ISINK = 10mA 4.5 5 70 2 1 0.1 1.3 0.1 100 5 2 1 5.5 150 5 3 1 2 2 400 10 5 3 V mV A mA A A VDCIN = 12V, VBATT = 16.8V 135 150 165 mV VDCIN = 18V DCIN = 0, VREFIN = 3.6V -1 IREF = 0A 0 < IREF < 500A VREF falling 2.5 1.9 50 50 100 +1 4.076 4.096 5 3.1 4.116 10 3.9 3.6 2.2 V mV V V V mV A CONDITIONS MIN TYP MAX UNITS
VDCIN = 19V, VBATT = 16.8V VDCIN = 18V, VBATT = 16.8V VDCIN = 18V, VBATT = 16.8V VDCIN = 12V, VBATT = 16.8V VDCIN = 12V, VBATT = 16.8V
135 2.2 0.15 1.6 0.15
150 2.4 0.4 1.8 0.3
165 2.6 0.50 2.0 0.40
mV s s s s
4
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Step-Up/Step-Down Li+ Battery Charger
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER GMS Amplifier Loop Transconductance CCV Output Current CCI Output Current CONDITIONS VCLS = REF, VCSSP - VCSSN = 102mV, VCSSP = VCSSS VCLS = REF, VCSSP - VCSSS = 102mV, VCSSP = VCSSN VCTL = REFIN, VBATT = 15.8V VCTL = REFIN, VBATT = 17.8V ICTL = REFIN, VCSIP - VCSIN = 0mV ICTL = REFIN, VCSIP - VCSIN = 150mV CLS = REF, VCSSP = VCSSN, VCSSP = VCSSS CCS Output Current CLS = REF, VCSSP - VCSSN = 200mV, VCSSP - VCSSS = 200mV 1.1V < VCCV < 3.5V, 1.1V < VCCS < 3.5V, 1.1V < VCCI < 3.5V VIINP = GND, ISINK = 1mA VIINP = 4V, ISOURCE = 1mA VIINP rising Hysteresis VSHDN = 0 to VREFIN DCIN = 0, VREFIN = 5V, VSHDN = 0 to VREFIN SHDN falling, VREFIN = 2.8V to 3.6V -1 -1 22 23.5 1 0.75 40 REFIN 0.75V CELLS = 0 to REFIN -2 +2 50 60 LDO 0.5 1.1 1.15 50 +1 +1 25 1.2 100 300 100 -100 500 A 150 -150 MIN 1.2 1.2 50 -50 TYP 1.7 1.7 MAX 2.2 2.2 UNITS A/mV A A
MAX1870A
CCI/CCS/CCV Clamp Voltage LOGIC LEVELS ASNS Output-Voltage Low ASNS Output-Voltage High ASNS Current Detect SHDN Input Bias Current SHDN Threshold SHDN Hysteresis CELLS Input Low Voltage CELLS Float Voltage CELLS Input High Voltage CELLS Input Bias Current
mV
0.4
V V V mV A % of REFIN % of REFIN V % of REFIN V A
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5
Step-Up/Step-Down Li+ Battery Charger MAX1870A
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = -40C to +85C.) (Note 1)
PARAMETER CHARGE-VOLTAGE REGULATION VCTL Range VVCTL = VLDO (2 cells) VVCTL = VLDO (3 cells) VVCTL = VLDO (4 cells) Battery Regulation Voltage Accuracy VVCTL = VREFIN (2 cells) VVCTL = VREFIN (3 cells) VVCTL = VREFIN (4 cells) VVCTL = VREFIN / 20 (2 cells) VVCTL = VREFIN / 20 (3 cells) VVCTL = VREFIN / 20 (4 cells) VCTL Default Threshold ICTL Range VICTL = VREFIN Quick-Charge-Current Accuracy BATT/CSIP/CSIN Input Voltage Range CSIP Input Current ICTL Power-Down-Mode Threshold Voltage INPUT-CURRENT REGULATION Charger-Input Current-Limit Accuracy (VCSSP - VCSSN) System-Input Current-Limit Accuracy (VCSSP - VCSSS) CSSP/CSSS/CSSN Input Voltage Range CSSP Input Current CLS Input Range IINP Transconductance IINP Output Current IINP Output Voltage VCSSP - VCSSS = 102mV, CSSN = CSSP VCSSP - VCSSN = 200mV, VIINP = 0V VCSSP - VCSSS = 200mV, VIINP = 0V VCSSP - VCSSN = 200mV, IINP float VCSSP - VCSSS = 200mV, IINP float VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V VREF / 2 2.5 350 350 3.5 3.5 CSSS = CSSP CSSN = CSSP CLS = REF CLS = REF x 0.845 CLS = REF CLS = REF x 0.845 95 79 95 79 8 115 97 115 97 28 1200 VREF 3.1 mV mV V A V A/mV A V ICTL = REFIN REFIN / 100 VICTL = VREFIN x 0.8 VICTL = VREFIN x 0.583 VCTL rising CHARGE-CURRENT REGULATION 0 66 53 38 0 3.6 80 65 48 19 600 REFIN / 32 V A V mV V 0 -0.8 -0.8 -0.8 -1.2 -1.2 -1.2 -1.4 -1.4 -1.4 4.0 3.6 +0.8 +0.8 +0.8 +1.2 +1.2 +1.2 +1.4 +1.4 +1.4 4.2 V % V CONDITIONS MIN TYP MAX UNITS
6
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Step-Up/Step-Down Li+ Battery Charger
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = -40C to +85C.) (Note 1)
PARAMETER SUPPLY AND LINEAR REGULATOR DCIN Input Voltage Range DCIN Undervoltage Lockout DCIN Quiescent Current BATT Input Voltage Range BATT Input Bias Current LDO Output Voltage LDO Undervoltage Lockout REFERENCE REF Output Voltage REF Load Regulation REF Undervoltage-Lockout Trip Point REFIN Input Range REFIN UVLO Rising REFIN Input Bias Current SWITCHING REGULATOR Cycle-by-Cycle Step-Up Maximum VDCIN = 12V, VBATT = 16.8V Current-Limit Sense Voltage Cycle-by-Cycle Step-Down Maximum Current-Limit Sense Voltage Step-Down On-Time Minimum Step-Down Off-Time Step-Up Off-Time Minimum Step-Up On-Time MOSFET DRIVERS VHP - VHN Output Voltage VHN Load Regulation DHI On-Resistance High DHI On-Resistance Low VHP Input Bias Current BLKP Input Bias Current DLOV Supply Current DBST On-Resistance High DBST On-Resistance Low 8V < VVHP < 28V, no load 0 < IVHN < 10mA ISOURCE = 10mA ISINK = 10mA VDCIN = 18V VICTL = VREFIN = 3.3V DBST low ISOURCE = 10mA ISINK = 10mA 4.5 5.5 150 5 3 2 400 10 5 3 V mV mA A A VDCIN = 19V, VBATT = 16.8V VDCIN = 18V, VBATT = 16.8V VDCIN = 18V, VBATT = 16.8V VDCIN = 12V, VBATT = 16.8V VDCIN = 12V, VBATT = 16.8V 130 170 mV VDCIN = 18V IREF = 0A 0 < IREF < 500A VREF falling 2.5 4.060 4.132 10 3.9 3.6 2.2 100 V mV V V V A VBATT = 2V to 19V No load VDCIN = 8V, LDO rising 5.3 4.00 DCIN falling DCIN rising 8.0V < VDCIN < 28V 0 8 4 7.85 6 19 500 5.5 5.25 28 V V mA V A V V CONDITIONS MIN TYP MAX UNITS
MAX1870A
130 2.2 0.15 1.6 0.15
170 2.6 0.50 2.0 0.40
mV s s s s
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7
Step-Up/Step-Down Li+ Battery Charger MAX1870A
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = -40C to +85C.) (Note 1)
PARAMETER ERROR AMPLIFIERS GMV Amplifier Loop Transconductance GMI Amplifier Loop Transconductance GMS Amplifier Loop Transconductance CCV Output Current CCI Output Current VCTL = REFIN, VBATT = 16.8V ICTL = REFIN, VCSIP - VCSIN = 72mV VCLS = REF, VCSSP - VCSSN = 102mV, VCSSP = VCSSS VCLS = REF, VCSSP - VCSSS = 102mV, VCSSP = VCSSN VCTL = REFIN, VBATT = 15.8V VCTL = REFIN, VBATT = 17.8V ICTL = REFIN, VCSIP - VCSIN = 0mV ICTL = REFIN, VCSIP - VCSIN = 150mV CLS = REF, VCSSP = VCSSN, VCSSP = VCSSS CCS Output Current CLS = REF, VCSSP - VCSSN = 200mV, VCSSP - VCSSS = 200mV 1.1V < VCCV < 3.5V, 1.1V < VCCS < 3.5V, 1.1V < VCCI < 3.5V VIINP = GND, ISINK = 1mA VIINP = 4V, ISOURCE = 1mA VIINP rising SHDN falling, VREFIN = 2.8V to 3.6V LDO 0.5 1.1 22 1.15 1.2 25 0.75 40 REFIN 0.75V 60 100 100 -100 500 A 150 -150 0.05 1.8 1.2 1.2 50 -50 0.20 3.0 2.2 2.2 A/mV A/mV A/mV A A CONDITIONS MIN TYP MAX UNITS
CCI/CCS/CCV Clamp Voltage LOGIC LEVELS ASNS Output-Voltage Low ASNS Output-Voltage High ASNS Current Detect SHDN Threshold CELLS Input Low Voltage CELLS Float Voltage CELLS Input High Voltage
mV
0.4
V V V % of REFIN V % of REFIN V
Note 1: Specifications to -40C are guaranteed by design, not production tested.
8
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Step-Up/Step-Down Li+ Battery Charger MAX1870A
Typical Operating Characteristics
(Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA = +25C, unless otherwise noted.)
BATTERY INSERTION AND REMOVAL
MAX1870Atoc01
BATTERY-REMOVAL RESPONSE
20V RCV = 10k, COUT = 22F 18V VBATT 16V ICHARGE 5A/div 0 RCV = 10k, COUT = 44F
MAX1870Atoc02
BATTERY REMOVAL BATTERY INSERTION
21V 20V 19V VBATT 18V 17V 16V
CCV CCI CCI CCV
RCV = 20k, COUT = 44F 4V CCI AND CCV 2V 0 10.0s/div
2.00ms/div
SYSTEM LOAD-TRANSIENT RESPONSE
MAX1870Atoc03
SYSTEM LOAD-TRANSIENT RESPONSE
MAX1870Atoc04 MAX1870Atoc06
5A SYSTEM LOAD 0A 4A 2A INDUCTOR CURRENT 0A 5A INPUT CURRENT 0A 2A BATTERY CURRENT 0A HYBRID MODE
5A SYSTEM LOAD 0A 4A 2A INDUCTOR CURRENT 0A 5A INPUT CURRENT 0A 2A BATTERY CURRENT 0A
STEP-DOWN MODE
200s
100s
CHARGE-CURRENT STEP RESPONSE
MAX1870Atoc05
CHARGE-CURRENT STEP RESPONSE
5V VICTL 0V 2A INDUCTOR CURRENT 0A HYBRID MODE 1V CCI 0V 2A BATTERY CURRENT 0A 1V CCI 0V 2A BATTERY CURRENT 0A 5V VICTL 0V 2A INDUCTOR CURRENT 0A
STEP-DOWN MODE
400s
400s
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9
Step-Up/Step-Down Li+ Battery Charger MAX1870A
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. BATTERY VOLTAGE
MAX1870A toc07
EFFICIENCY vs. CHARGE CURRENT
VBATT = 16.8V
MAX1870A toc08
BATTERY VOLTAGE ERROR IN CV MODE
0.4 BATTERY VOLTAGE ERROR (%) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 VBATT = 8.4V VBATT = 16.8V VBATT = 12.6V
MAX1870A toc09
95 90 85 EFFICIENCY (%) VIN = 12V
100 95 90 EFFICIENCY (%)
0.5
80 75 70 65 60 2 4 6
VIN = 16V
85 80 75 70 65 60 VBATT = 8.4V
VBATT = 12.6V
8
10
12
14
16
18
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
BATTERY VOLTAGE (V)
CHARGE CURRENT (A)
CHARGE CURRENT (A)
BATTERY VOLTAGE ERROR vs. VCTL
MAX1870Atoc10
CHARGE-CURRENT ERROR vs. ICTL
MAX1870Atoc11
CHARGE-CURRENT ERROR vs. BATTERY VOLTAGE
ICHG = 0.15A CHARGE-CURRENT ERROR (%) 10 ICHG = 2.4A 5 0 ICHG = 1.9A -5 -10 -15 ICHG = 1.4A
MAX1870Atoc12
0.25
20 10 CHARGE-CURRENT ERROR (mA) 0 -10 -20 -30 -40 -50 -60 -70
15
BATTERY VOLTAGE ERROR (%)
0.20
0.15
0.10
0.05
0 0 1.00 2.00 VCTL (V) 3.00 4.00
-80 0 0.50 1.00 1.50 VICTL (V) 2.00 2.50 3.00
0
5
10 VBATT (V)
15
20
IINP ERROR vs. SYSTEM LOAD
MAX1870Atoc13
INPUT CURRENT-LIMIT ERROR vs. SYSTEM CURRENT
MAX1870A toc14
INPUT CURRENT-LIMIT ERROR vs. CLS
150 100 50 0 -50 -100 -150 -200 -250 -300
MAX1870A toc15
5 4 3 IINP ERROR (mV) 2 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
10 8 INPUT CURRENT-LIMIT ERROR (%) 6 4 2 0 -2 -4 -6 -8 -10 VBATT = 16V VBATT = 12V 0 0.5 1.0 1.5 2.0 2.5 3.0 VBATT = 14V VBATT = 10V VBATT = 8V VBATT = 6V
200 INPUT CURRENT-LIMIT ERROR (mA)
4.0
3.5
0
1.00
2.00
3.00
4.00
5.00
SYSTEM LOAD (A)
SYSTEM CURRENT (A)
VCLS (V)
10
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Step-Up/Step-Down Li+ Battery Charger MAX1870A
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA = +25C, unless otherwise noted.)
REF LOAD REGULATION
MAX1870A toc16
REFERENCE ERROR vs. TEMPERATURE
MAX1870Atoc17
LDO LOAD REGULATION
MAX1870A toc18
4.11 4.10 4.09 VREF (V) 4.08 4.07 4.06 4.05 4.04 4.03 0 500 1000 1500 2000
0.45 0.40 REFERENCE ERROR (%) 0.35 0.30
5.38 5.36 VIN = 28V 5.34 VLDO (V) 5.32 5.30 5.28 VIN = 9V 5.26 5.24 VIN = 16V
0.25 0.20 0.15 0.10 0.05 0
2500
-40
-20
0
20
40
60
80
100
0
10
20
30
40
50
LOAD CURRENT (A)
TEMPERATURE (C)
LOAD (mA)
LDO vs. TEMPERATURE
MAX1870A toc19
OUTPUT VOLTAGE RIPPLE vs. BATTERY VOLTAGE
160 RMS OUTPUT RIPPLE (mV) 140 120 100 80 60 40
MAX1870Atoc20
0.8 0.6 LDO VOLTAGE ERROR (%) 0.4 0.2 0 -0.2 -0.4 -40 -20 0 20 40 60 80
180
20 0 100 0 5 10 VBATT (V) 15 20 TEMPERATURE (C)
STEP-UP/STEP-DOWN SWITCHING WAVEFORM
MAX1870Atoc21
STEP-DOWN SWITCHING WAVEFORM
MAX1870Atoc22
20V 10V D4 CATHODE 0V 10V D3 ANODE 0V 4A INDUCTOR CURRENT 2A VBATT (AC-COUPLED) 200mV/div VIN = 16V VBATT = 12V
20V 10V D4 CATHODE 0V 10V D3 ANODE 0V 4A INDUCTOR CURRENT 2A VBATT (AC-COUPLED) 10mV/div
VIN = 16V VBATT = 16V
2.00s
2.00s
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11
Step-Up/Step-Down Li+ Battery Charger MAX1870A
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA = +25C, unless otherwise noted.)
STEP-UP SWITCHING WAVEFORM
MAX1870Atoc23
STEP-UP/STEP-DOWN LIGHT LOAD
10V D4 CATHODE 0V 10V D3 ANODE 0V 4A INDUCTOR CURRENT 2A VBATT (AC-COUPLED) 50mV/div CHARGE CURRENT = 300mA
MAX1870Atoc24
20V VIN = 16V VBATT = 16V
20V 10V D4 CATHODE 0V 10V D3 ANODE 0V 4A INDUCTOR CURRENT 2A VBATT (AC-COUPLED) 50mV/div
VIN = 12V VBATT = 16V
2.00s
2.00s
Pin Description
PIN 1 2 3 4, 8 5 6 7 9 10 11 NAME LDO REF CLS GND CCV CCI CCS REFIN ASNS VCTL FUNCTION Device Power Supply. Output of the 5.4V linear regulator supplied from DCIN. Bypass LDO to GND with a 1F or greater ceramic capacitor. 4.096V Voltage Reference. Bypass REF to GND with a 1F or greater ceramic capacitor. Source Current-Limit Input. Voltage input for setting the current limit of the input source. See the Setting the Input Current Limit section. Analog Ground Voltage Regulation Loop Compensation Point. Connect a 10k resistor in series with a 0.01F capacitor to GND. Charge-Current Regulation Loop Compensation Point. Connect a 0.01F capacitor to GND. Input-Current Regulation Loop Compensation Point. Connect a 0.01F capacitor to GND. Reference Input. ICTL and VCTL are ratiometric with respect to REFIN for increased accuracy. Adapter Sense Output. Logic output is high when input current is greater than 1.5A (using 30m sense resistors and a 10k resistor from IINP to GND). Charge-Voltage Control Input. Drive VCTL from 0 to VREFIN to adjust the charge voltage from 4V to 4.4V per cell. See the Setting the Charge Voltage section.
12
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Step-Up/Step-Down Li+ Battery Charger
Pin Description (continued)
PIN 12 13 NAME ICTL CELLS FUNCTION Charge-Current Control Input. Drive ICTL from VREFIN / 32 to VREFIN to adjust the charge current. See the Setting the Charge Current section. Drive ICTL to GND to disable charging. Cell-Count Selection Input. Connect CELLS to GND for two Li+ cells. Float CELLS for three Li+ cells, or connect CELLS to REFIN for four Li+ cells. Input-Current Monitor Output. IINP is a replica of the input current sensed by the MAX1870. It represents the sum of the current consumed by the charger and the current consumed by the system. IINP has a transconductance of 2.8A/mV. Shutdown Comparator Input. Pull SHDN low to stop charging. Optionally connect a thermistor to stop charging when the battery temperature is too hot. Battery-Voltage Feedback Input Charge Current-Sense Negative Input Charge Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN. Connect a 2.2F capacitor from CSIP to GND. Power Connection for Current-Sense Amplifier. Connect BLKP to BATT. Internally Connected. Do not connect this pin. Step-Up Power MOSFET (NMOS) Gate-Driver Output Power Ground Internally Connected. Do not connect this pin. Low-Side Driver Supply. Bypass DLOV with a 1F capacitor to GND. Power Connection for the High-Side MOSFET Driver. Bypass VHP to VHN with a 1F or greater ceramic capacitor. High-Side Power MOSFET (PMOS) Driver Output. Connect to the gate of the high-side step-down MOSFET. Power Connection for the High-Side MOSFET Driver. Bypass VHP to VHN with a 1F or greater ceramic capacitor. Negative Terminal for Current-Sense Resistor for Charger Current. Connect a 2.2F capacitor from CSSN to GND. Negative Terminal for Current-Sense Resistor for System Load Current Positive Terminal for Input Current-Sense Resistors. Connect a current-sense resistor from CSSP to CSSN. Connect an equivalent sense resistor from CSSP to CSSS. DC Supply Voltage Input. Bypass DCIN with a 1F or greater ceramic capacitor to power ground. Paddle. Connect to GND.
MAX1870A
14
IINP
15 16 17 18 19 20, 21 22 23 24 25 26 27 28 29 30 31 32 Paddle
SHDN BATT CSIN CSIP BLKP I.C. DBST PGND I.C. DLOV VHN DHI VHP CSSN CSSS CSSP DCIN
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13
Step-Up/Step-Down Li+ Battery Charger MAX1870A
OPTIONAL REVERSEADAPTER PROTECTION D2 + AC ADAPTER 32 C5 1F D1 30 CSSS DCIN 28 VHP VHN CSSP 26 RS1a 30m 31 SYSTEM LOAD 2.2F 2 C1 1F R3 3 CLS REF CSSN 29 M1 RS1b 30m C7 1F C8 22F
DHI
27
P
L1 10H
R4
MAX1870A
D4 M2 N D3
5 R5 10k C2 0.01F C3 0.01F C4 0.01F 6 7
CCV CCI CCS
DBST
22
CSIP
18 2.2F RS2 30m
HOST VDD DIGITAL INPUT D/A OUTPUT D/A OUTPUT HI-IMPEDANCE OUTPUT LOGIC OUTPUT A/D INPUT GND R7 10k
9 10
REFIN ASNS
CSIN BATT BLKP
17 16 C9 44F
11 VCTL 12 ICTL 13 CELLS 15 SHDN 14 C6 0.01F IINP
19
DLOV
25 R6 33 C11 1F C12 1F
LDO GND 4 PGND 23
1
Figure 1. C-Controlled Typical Application Circuit
14
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Step-Up/Step-Down Li+ Battery Charger MAX1870A
OPTIONAL REVERSEADAPTER PROTECTION OPTIONAL + AC ADAPTER 32 C5 1F 13 2 C1 1F R3 SHORT R4 OPEN D4 9 15 R9 OPEN R1 SHORT 11 LDO R10 OPEN 12 R12 OPEN CSIN ASNS BATT 14 R7 10k C6 0.01F 25 1 R6 33 C11 1F C12 1F IINP BLKP 19 C9 44F 17 16 DCIN D1 30 CSSS 28 VHP VHN CSSP 26 31 C7 1F RS1a 30m SYSTEM LOAD CELLS REF CSSN 29 2.2F RS1b 30m D2 C8 22F
3
CLS
DHI
27
M1
P
L1 10H
MAX1870A
REFIN SHDN DBST 22 M2 N D3
VCTL ICTL CSIP 18 2.2F RS2 30m
10
5 R5 10k C2 0.01F
CCV
DLOV LDO
C3 0.01F
CCI 6
CCS 7
C4 0.01F
GND 4
PGND 23
Figure 2. Stand-Alone Typical Application Circuit
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15
Step-Up/Step-Down Li+ Battery Charger MAX1870A
Detailed Description
The MAX1870A includes all of the functions necessary to charge Li+, NiMH, and NiCd batteries. A high-efficiency H-bridge topology DC-DC converter controls charge voltage and current. A proprietary control scheme offers improved efficiency and smaller inductor size compared to conventional H-bridge controllers and operates from input voltages above and below the battery voltage. The MAX1870A includes analog control inputs to limit the AC adapter current, charge current, and battery voltage. An analog output (IINP) delivers a current proportional to the source current. The Typical Application Circuit shown in Figure 1 uses a microcontroller (C) to control the charge current or voltage, while Figure 2 shows a typical application with the charge voltage and current fixed to specific values for the application. The voltage at ICTL and the value of RS2 set the charge current. The voltage at VCTL and the CELLS inputs set the battery regulation voltage for the charger. The voltage at CLS and the value of R3 and R4 set the source current limit. The MAX1870A features a voltage-regulation loop (CCV) and two current-regulation loops (CCI and CCS). CCV is the compensation point for the battery voltage regulation loop. CCI and CCS are the compensation points for the battery charge current and supply current loops, respectively. The MAX1870A regulates the adapter current by reducing battery charge current according to system load demands.
Table 1. Cell-Count Programming Table
CELLS GND Float REFIN CELL COUNT 2 3 4
where NCELLS is the cell count selected by CELLS. VCTL is ratiometric with respect to REFIN to improve accuracy when using resistive voltage-dividers. Connect CELLS as shown in Table 1 to charge two, three, or four cells. The cell count can either be hardwired or software controlled. The internal error amplifier (GMV) maintains voltage regulation (see Figure 3 for the Functional Diagram). Connect a 10k resistor in series with a 0.01F capacitor from CCV to GND to compensate the battery voltage loop. See the Voltage Loop Compensation section for more information.
Setting the Charge Current
Set the maximum charge current using ICTL and the current-sense resistor RS2 connected between CSIP and CSIN. The current threshold is set by the ratio of VICTL / VREFIN. Use the following equation to program the battery charge current: ICHG = VCSIT V x ICTL RS2 VREFIN
Setting the Charge Voltage
The MAX1870A provides high-accuracy regulation of the charge voltage. Apply a voltage to VCTL to adjust the battery-cell voltage limit. Set VCTL to a voltage between 0 and VREFIN for a 10% adjustment of the battery cell voltage, or connect VCTL to LDO for a default setting of 4.2V per cell. The limited adjustment range reduces the sensitivity of the charge voltage to external resistor tolerances. The overall accuracy of the charge voltage is better than 1% when using 1% resistors to divide down the reference to establish VCTL. The percell battery-termination voltage is a function of the battery chemistry and construction. Consult the battery manufacturer to determine this voltage. Calculate battery voltage using the following equation: V VBATT = NCELLS x 4V + 0.4V x VCTL VREFIN
where V CSIT is the full-scale charge current-sense threshold, 73mV (typ). The input range for ICTL is VREFIN / 32 to VREFIN. To shut down the MAX1870A, force ICTL below VREFIN / 100. The internal error amplifier (GMI) maintains chargecurrent regulation (see Figure 3 for the Functional Diagram). Connect a 0.01F capacitor from CCI to GND to compensate the charge-current loop. See the ChargeCurrent Loop Compensation section for more information.
Setting the Input Current Limit
The total input current, from a wall adapter or other DC source, is a function of the system supply current and the battery charge current. The MAX1870A limits the wall adapter current by reducing the charge current when the input current exceeds the input current-limit set point. As the system supply current rises, the available charge current decreases linearly to zero in proportion to the system current. After the charge current has fallen to zero, the MAX1870A cannot further limit the wall adapter current if the system current continues to increase.
16
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Step-Up/Step-Down Li+ Battery Charger MAX1870A
IINP ASNS
CSSN A = 18V/V CURRENTSENSE AMPLIFIERS CSSP A = 18V/V CSSS GMS CLS CCS CSS
INPUT-CURRENT BLOCK
Gm IMAX1 3.6V (6.7A FOR 30m) 0.81mV (1.5A FOR 30m)
MAX1870A
LVC
CCI ICTL CSIP A = 18V/V CSI CSIN 22.5mV (42mA ON 30m) IZX IMAX1 STEP-UP/DOWN CURRENT-MODE STATE MACHINE LEVEL SHIFT LOWSIDE DRIVER CHG CCV VCTL x 400mV + 4.0V REFIN SHUTDOWN LOGIC 4.2V GMV ICTL SHDN VHN DLOV LVC IMIN HIGHSIDE DRIVER DHI VHP x 50mV REFIN GMI 0.15V
CHARGE-CURRENT BLOCK
DBST
(6.7A FOR 30m) 3.6V
IMAX2
23% OF REFIN
PGND
RDY GND REF BATT CELLSELECT LOGIC BATTERY-VOLTAGE BLOCK 5.4V LINEAR REGULATOR 4.096V REFERENCE 1/55 CELLS
DCIN
LDO
REF
REFIN
Figure 3. Functional Diagram
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17
Step-Up/Step-Down Li+ Battery Charger MAX1870A
The input source current is the sum of the MAX1870A quiescent current, the charger input current, and the system load current. The MAX1870A's 6mA maximum quiescent current is minimal compared to the charge and load currents. The actual wall adapter current is determined as follows: I x VBATT IADAPTER = ISYS _ LOAD + CHARGE VIN x where is the efficiency of the DC-DC converter (85% to 95% typ), I SYS_LOAD is the system load current, IADAPTER is the adapter current, and ICHARGE is the charge current. By controlling the input current, the current requirements of the AC wall adapter are reduced, minimizing system size and cost. Since charge current is reduced to control input current, priority is given to system loads. An internal amplifier compares the sum of (VCSSP VCSSN) and (VCSSP - VCSSS) to a scaled voltage set by the CLS input. Drive VCLS directly or set with a resistive voltage-divider between REF and GND. Connect CLS to REF for the maximum input current limit of 105mV. Sense resistors RS1a and RS1b set the maximumallowable wall adapter current. Use the same values for RS1a, RS1b, and RS2. Calculate the maximum wall adapter current as follows: IADAPTER _ MAX = VCLS V x CSST VREF RS1_ In the Typical Application Circuit, the duty cycle and AC load current affect the accuracy of VIINP (see the Typical Operating Characteristics).
LDO Regulator
LDO provides a 5.4V supply derived from DCIN. The low-side MOSFET driver is powered by DLOV, which must be connected to LDO as shown in Figure 1. LDO also supplies the 4.096V reference (REF) and most of the internal control circuitry. Bypass LDO to GND with a 1F or greater ceramic capacitor. Bypass DLOV to PGND with a 1F or greater ceramic capacitor.
AC Adapter Detection
The MAX1870A includes a logic output, ASNS, which indicates AC adapter presence. When the system load draws more than 1.5A (for 30m sense resistors and R7 is 10k), the ASNS logic output pulls high.
Shutdown
When the AC adapter is removed, the MAX1870A shuts down to a low-power state, and typically consumes less than 1A from the battery through the combined load of the CSIP, CSIN, BLKP, and BATT inputs. The charger enters this low-power state when DCIN falls below the undervoltage-lockout (UVLO) threshold of 7.5V. Alternatively, drive SHDN below 23.5% of VREFIN or drive ICTL below VREFIN / 100 to inhibit charge. This suspends switching and pulls CCI, CCS, and CCV to ground. The LDO, input current monitor, and control logic all remain active in this state.
where VCSST is the full-scale source current-sense voltage threshold, and is 105mV (typ). The internal error amplifier (GMS) maintains input-current regulation (see Figure 3 for the Functional Diagram). Typically, connect a 0.01F capacitor from CCS to GND to compensate the source current loop (GMS). See the Charge-Current and Wall-Adapter-Current Loop Compensation for more information.
Step-Up/Step-Down DC-DC Controller
The MAX1870A is a step-up/step-down DC-DC controller. The MAX1870A controls a low-side n-channel MOSFET and a high-side p-channel MOSFET to a constant output voltage with input voltage variation above, near, and below the output. The MAX1870A implements a patented control scheme that delivers higher efficiency with smaller components and less output ripple when compared with other step-up/step-down control algorithms. This occurs because the MAX1870A operates with lower inductor currents, as shown in Figure 4. The MAX1870A proprietary algorithm offers the following benefits: * Inductor current requirements are minimized. * Low inductor-saturation current requirements allow the use of physically smaller inductors. * Low inductor current improves efficiency by reducing I 2 R losses in the MOSFETs, inductor, and sense resistors.
Input Current Measurement
The MAX1870A includes an input-current monitor output, IINP. IINP is a scaled-down replica of the system load current plus the input-referred charge current. The output voltage range for IINP is 0 to 3.5V. The voltage of IINP is proportional to the output current by the following equation: VIINP = IADAPTER x RS1_ x GIINP x R7 where I ADAPTER is the DC current supplied by the AC adapter, G IINP is the transconductance of IINP (2.8A/mV typ), and R7 is the resistor connected between IINP and ground.
18
______________________________________________________________________________________
Step-Up/Step-Down Li+ Battery Charger
* Continuous output current for V IN > 1.4 x V OUT reduces output ripple. The MAX1870A uses the state machine shown in Figure 5. The controller switches between the states A, B, and C, depending on VIN and VBATT. State D provides PFM operation during light loads. Under moderate and heavy loads the MAX1870A operates in PWM. up with a dI/dt of (VIN - VBATT) / L. M1 remains on until a step-down on-time timer expires. This on-time is calculated based on the input and output voltage to maintain pseudo-fixed-frequency 400kHz operation. At the end of state B, another step-down off-time (state A) is initiated and the cycle repeats. The off-time is valley regulated according to the error signal. The error signal is set by the charge current or source current if either is at its limit, or the battery voltage if both charge current and source current are below their respective current limits. During light loads, when the inductor current falls to zero during state A, the controller switches to state D to reduce power consumption and avoid shuttling current in and out of the output.
MAX1870A
Step-Down Operation (VIN > 1.4 x VBATT)
During medium and heavy loads when V IN > 1.4 x VBATT, the MAX1870A alternates between state A and state B, keeping MOSFET M2 off (Figure 5). Figure 6 shows the inductor current in step-down operation. During this mode, the MAX1870A regulates the stepdown off-time. Initially, DHI switches M1 off (state A) and the inductor current ramps down with a dI/dt of VBATT / L until a target current is reached (determined by the error integrator). After the target current is reached, DHI switches M1 on (state B), and the inductor current ramps
Step-Up Operation (VIN < 0.9 x VBATT)
When V IN < 0.9 x V BATT, the MAX1870A alternates between state B and state C, keeping MOSFET M1 on. In this mode, the controller looks like a simple step-up controller. Figure 7 shows the inductor current in step-
Table 2. MAX1870A H-Bridge Controller Advantages
MAX1870A H-BRIDGE CONTROLLER * * Only 1 MOSFET switched per cycle Continuous output current in step-down mode * * TRADITIONAL H-BRIDGE CONTROLLER 2 MOSFETs switched per cycle Always discontinuous output current (requires higher inductor currents)
A) CONVENTIONAL ALGORITHM
2 x ICHARGE
B) MAX1870A ALGORITHM SHADED REGIONS REPRESENT CHARGE DELIVERED
TIME
Figure 4. Inductor Current for VIN = VBATT
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19
Step-Up/Step-Down Li+ Battery Charger
up operation. During this mode, the MAX1870A regulates the step-up on-time. Initially DBST switches M2 on (state C) and the inductor current ramps up with a dI/dt of VIN / L. After the inductor current crosses the target current (set by the error integrators), DBST switches M2 off (state B) and the inductor current ramps down with a dI/dt of (VBATT - VIN) / L. M2 remains off until a stepup off-time timer expires. This off-time is calculated based on the input and output voltage to maintain 400kHz pseudo-fixed-frequency operation. The step-up on-time is regulated by the error signal, set according to the charge current or source current if either is at its limit, or the battery voltage if both charge current and source current are below their respective current limits. states A, B, and C, following the order A, B, C, B, A, B, C, etc., with the majority of the time spent in state B. Since more time is spent in state B, the inductor ripple current is reduced, improving efficiency. The time in state C is peak-current regulated, and the remaining time is spent in state B (Figure 8A). During this operating mode, the average inductor current is approximately 20% higher than the load current. The time in state A is valley current and the remaining time is spent in state B (Figure 8B). During this mode, the average inductor current is approximately 10% higher than the load current. Alternative algorithms require inductor currents twice as high, resulting in four times larger I2R losses and inductors typically four times larger in volume.
MAX1870A
Step-Up/Step-Down Operation (0.9 x VBATT < VIN < 1.4 x VBATT)
The MAX1870A features a step-up/step-down mode that eliminates dropout. Figure 8 shows the inductor current in step-up/step-down operation. When V IN is within 10% of VBATT, the MAX1870A alternates through
IMIN, IMAX, CCMP, and ZCMP
The MAX1870A state machine utilizes five comparators to decide which state to be in and when to switch states (Figure 3). The MAX1870A generates an error
STATE A
STATE B
STATE C
STEP-DOWN OFF VIN VOUT D3 STEP-DOWN PWM M2 VIN
STEP-DOWN ON VOUT D3 STEP-UP PWM M2 VIN VOUT
M1
M1
M1
D3 + -
D4
D4
D4
M2
STEP-UP OFF STEP-DOWN PFM VIN VOUT D3
STEP-UP ON
M1
D2
M2
IDLE STATE D
Figure 5. MAX1870A State Machine 20 ______________________________________________________________________________________
Step-Up/Step-Down Li+ Battery Charger MAX1870A
dl VIN - VOUT = L dt STATE B
dl VOUT = L dt
STATE A
VALLEY REGULATED OFF-TIME PRECALCULATED STEP-DOWN ON-TIME VIN > 1.4 x VBATT DUTY = VIN / VOUT
Figure 6. MAX1870A Step-Down Inductor Current Waveform
STATE B
dl VIN - VOUT = L dt
PEAK REGULATED ON-TIME
STATE C
dl VOUT = L dt
PRECALCULATED OFF-TIME
VIN > 0.9 x VBATT
DUTY = 1 - VIN / VOUT
Figure 7. Step-Up Inductor-Current Waveform
signal based on the integrated error of the input current, charge current, and battery voltage. The error signal, determined by the lowest voltage clamp (LVC), sets the threshold for current-mode regulation. The following comparators are used for regulation: IMIN: The MAX1870A operates in discontinuous conduction if LVC is below 0.15V, and does not initiate another step-down on-time. In discontinuous step-up conduction, the peak current is set by IMIN. The peak
inductor current in discontinuous step-up mode is: IPK > VIMIN ACSI x RS2
where VIMIN is the IMIN comparator threshold, 0.15V, and ACSI is the charge current-sense amplifier gain, 18V/V. CCMP: CCMP compares the current-mode control
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21
Step-Up/Step-Down Li+ Battery Charger
point, LVC, to the inductor current. In step-down mode, the off-time (state A) is terminated when the inductor current falls below the current threshold set by LVC. In step-up mode, the on-time (state C) is terminated when the inductor current rises above the current threshold set by LVC. IMAX: The IMAX comparators provide a cycle-by-cycle inductor current limit. This circuit compares the inductor current (CSI in step-down mode or CSS in step-up mode) to the internally fixed cycle-by-cycle current limit. The current-sense voltage limit is 200mV. With RS1_ = RS2 = 30m, which corresponds to 6.7A. If the inductor current-sense voltage is greater than VIMAX
MAX1870A
(200mV), a step-up on-time is terminated or a stepdown on-time is not permitted. ZCMP: The ZCMP comparator detects when the inductor current crosses zero. If the ZCMP output goes high during a step-down off-time, the MAX1870A switches to the idle state (state D) to conserve power.
Switching Frequency
The MAX1870A includes input and output-voltage feedforward to maintain pseudo-fixed-frequency (400kHz) operation. The time in state B is set according to the input voltage, output voltage, and a time constant. In step-up/step-down mode the switching frequency is
PEAK REGULATED STEP-UP ON-TIME
MINIMUM STEP-DOWN OFF-TIME
STATE B A) STATE C STATE A
STATE B
MINIMUM STEP-UP ON-TIME
PRECALCULATED STEP-DOWN ON-TIME
PRECALCULATED STEP-UP OFF-TIME
STATE B dl VBATT - VIN = L dt B) STATE A V dl = IN L dt STATE B dl VBATT = L dt
STATE C
VALLEY REGULATED STEP-DOWN OFF-TIME
PRECALCULATED STEP-DOWN ON-TIME
Figure 8. MAX1870A Step-Up/Step-Down Inductor-Current Waveform 22 ______________________________________________________________________________________
Step-Up/Step-Down Li+ Battery Charger
effectively cut in half to allow for both the step-up cycle and the step-down cycle. The switching frequency is typically between 350kHz and 405kHz for VIN between 8V and 28V. See the Typical Operating Characteristics.
MAX1870A
LTF = GMPWM x
ROGMV x (1 + sCCV RCV) x (1 + sCCV x ROGMV)
Compensation
Each of the three regulation loops (the battery voltage, the charge current, and the input current limit) are compensated separately using the CCV, CCI, and CCS pins, respectively. Compensate the voltage regulation loop with a 10k resistor in series with a 0.01F capacitor from CCV to GND. Compensate the charge current loop and source current loop with 0.01F capacitors from CCI to GND and from CCS to GND, respectively. Voltage Loop Compensation When regulating the charge voltage, the MAX1870A behaves as a current-mode step-down or step-up power supply. Since a current-mode controller regulates its output current as a function of the error signal, the duty-cycle modulator can be modeled as a GM stage (Figure 9). Results are similar in step-down, step-up, or step-up/down, with the exception of a load-dependent right-half-plane zero that occurs in step-up mode. The required compensation network is a pole-zero pair formed with CCV and RCV. CCV is chosen to be large enough that its impedance is relatively small compared to RCV at frequencies near crossover. RCV sets the gain of the error amplifier near crossover. R CV and COUT determine the crossover frequency and, therefore, the closed-loop response of the system and the response time upon battery removal. RESR is the equivalent series resistance (ESR) of the charger's output capacitor (COUT). RL is the equivalent charger output load, RL = VBATT / ICHG = RBATT. The equivalent output impedance of the GMV amplifier, R OGMV , is greater than 10M. The voltage loop transconductance (GMV = I CCV / V BATT ) scales inversely with the number of cells. GMV = 0.1A/mV for four cells, 0.133A/mV for three cells, and 0.2A/mV for two cells. The DC-DC converter's transconductance depends upon the charge current-sense resistor RS2: GMPWM = ACSI 1 x RS2
RL x GMV x (1 + sCOUT x RESR) (1 + sCOUT x RL) The poles and zeros of the voltage-loop transfer function are listed from lowest frequency to highest frequency in Table 3. Near crossover, CCV has much lower impedance than ROGMV. Since CCV is in parallel with ROGMV, CCV dominates the parallel impedance near crossover. Additionally, RCV has a much higher impedance than CCV and dominates the series combination of RCV and CCV, so: ROGMV x (1 + sCCV x RCV) RCV, near crossover (1 + sCCV x ROGMV) COUT also has a much lower impedance than RL near crossover, so the parallel impedance is mostly capacitive and: 1 RL (1 + sCOUT x RL) sCOUT If RESR is small enough, its associated output zero has a negligible effect near crossover and the loop transfer function can be simplified as follows:
BATT GMOUT
RESR COUT
RL
CCV GMV
where A CSI = 18, and RS2 = 30m in the Typical Application Circuits, so GMPWM = 1.85A/V. Use the following equation to calculate the loop transfer function (LTF):
RCV CCV
RO REF
Figure 9. CCV Simplified Loop Diagram ______________________________________________________________________________________ 23
Step-Up/Step-Down Li+ Battery Charger MAX1870A
LTF = GMPWM x RCV GMV sCOUT RL = 0.2 RCV = fOSC = 400kHz 2 x COUT x fCO _ CV = 10k GMV x GMPWM
Setting the LTF = 1 to solve for the unity-gain frequency yields: RCV fCO _ CV = GMPWM x GMV 2 x COUT For stability, choose a crossover frequency lower than 1/10th of the switching frequency. The crossover frequency must also be below the RHP zero, calculated at maximum charge current, minimum input voltage, and maximum battery voltage. Choosing a crossover frequency of 13kHz and solving for RCV using the component values listed in Figure 1 yields: MODE = VCC (4 cells) GMV = 0.1A/mV COUT = 22F GMPWM = 1.85A/V VBATT= 16.8V fCO_CV = 13kHz
To ensure that the compensation zero adequately cancels the output pole, select fZ_CV fP_OUT. CCV (RL / RCV) x COUT CCV 440pF Figure 10 shows the Bode Plot of the voltage-loop frequency response using the values calculated above. Charge-Current and Wall-Adapter-Current Loop Compensation When the MAX1870A regulates the charge current or the wall adapter current, the system stability does not depend on the output capacitance. The simplified schematic in Figure 11 describes the operation of the MAX1870A when the charge-current loop (CCI) is in control. The simplified schematic in Figure 12 describes the operation of the MAX1870A when the source-current
Table 3. Constant Voltage Loop Poles and Zeros
NO. 1 NAME CCV Pole CALCULATION DESCRIPTION Lowest Frequency Pole created by CCV and GMV's finite output resistance. Since ROGMV is very large (ROGMV > 10M), this is a low-frequency pole. Voltage-Loop Compensation Zero. If this zero is lower than the output pole, fP_OUT, then the loop transfer function approximates a single-pole response near the crossover frequency. Choose CCV to place this zero at least 1 decade below crossover to ensure adequate phase margin. Output Pole Formed with the Effective Load Resistance RL and the Output Capacitance COUT. RL influences the DC gain but does not affect the stability of the system or the crossover frequency. Output ESR Zero. This zero can keep the loop from crossing unity gain if fZ_OUT is less than the desired crossover frequency. Therefore, choose a capacitor with an ESR zero greater than the crossover frequency. Step-Up Mode RHP Zero. This zero occurs because of the initial opposing response of a step-up converter. Efforts to increase the inductor current result in an immediate decrease in current delivered, although eventually result in an increase in current delivered. This zero is dependent on charge current and may cause the system to go unstable at high currents when in step-up mode. A right-half-plane zero is detrimental to both phase and gain. To ensure stability under maximum load in step-up mode, the crossover frequency must be lower than half of fRHPZ.
fP _ CV =
1 2 x ROGMV CCV
2
CCV Zero
fZ _ CV =
1 2 x RCV CCV 1 2 x RL COUT 1 2 x RESR COUT
3
Output Pole
fP _ OUT =
4
Output Zero
fZ _ OUT =
fRHPZ =
5 RHP Zero
VIN 2 x L IL VIN2 = 2 x L IOUT VOUT
24
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Step-Up/Step-Down Li+ Battery Charger
loop (CCS) is in control. Since the output capacitor's impedance has little effect on the response of the current loop, only a single pole is required to compensate this loop. ACSI and ACSS are the internal gains of the currentsense amplifiers. RS2 is the charge current-sense resistor. RS1a and RS1b are the adapter current-sense resistors. ROGMI and ROGMS are the equivalent output impedance of the GMI and GMS amplifiers, which are greater than 10M. GMI is the charge-current amplifier transconductance (2.4A/mV). GMS is the adapter-current amplifier transconductance (1.7A/mV.) GMPWM is the DC-DC converter transconductance (1.85A/V). Use the following equation to calculate the loop transfer function:
LTF = GMPWM x ACS _ x RS _ x GM _ ROGM _ 1 + sROGM _ x CC _
For stability, choose a crossover frequency lower than 1/10th of the switching frequency and lower than half of the RHP zero. CCI = 10 GMI / (2 x fOSC), CCS = 10 GMS / (2 x fOSC) fRHPZ _ WorstCase = VIN _ MIN VIN _ MIN2 = 2 x L IL 2 L IOUTMAX VOUTMAX
MAX1870A
which describes a single-pole system. Since GMPWM = 1 ACS _ x RS _ the loop-transfer function simplifies to: LTF = GM _ ROGM _ 1 + sROGM _ x CC _
This zero is inversely proportional to charge current and may cause the system to go unstable at high currents when in step-up mode. A right-half-plane zero is detrimental to both phase and gain. To also ensure stability under maximum load in step-up mode, the CCI crossover frequency must also be lower than f RHPZ. The right-half-plane zero does not affect CCS. Choosing a crossover frequency of 30kHz and using the component values listed in Figure 1 yields CCI and CCS_ > 10nF. Values for CCI / CCS greater than ten times the minimum value may slow down the current loop response excessively. Figure 13 shows the Bode Plot of the input-current frequency response using the values calculated above.
MOSFET Drivers
DHI and DBST are optimized for driving moderatelysized power MOSFETs. Use low-inductance and lowresistance traces from driver outputs to MOSFET gates. DHI typically sources 1.6A and sinks 0.8A to or from the gate of the p-channel MOSFET. DHI swings from VHP to VHN. VHN is a negative LDO that regulates with respect to VHP to provide high-side gate drive. Connect VHP to DCIN. Bypass VHN with a 1F capacitor to VHP.
Use the following equations to calculate the crossover frequency: fCO _ CI = GMI GMS , fCO _ CS = 2CCI 2CCS
CCV LOOP RESPONSE
80 60 MAG MAGNITUDE (dB) 40 PHASE 20 0 -20 CCI -40 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 FREQUENCY (Hz) -135 ROGMI REF -90 CSI GMI -45 ACSI 0 GMPWM RS2
CCI
Figure 10. CCV Loop Response
Figure 11. CCI Simplified Loop Diagram 25
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Step-Up/Step-Down Li+ Battery Charger MAX1870A
LDO provides a 5.4V supply derived from DCIN and delivers over 10mA. The n-channel MOSFET driver DBST is powered by DLOV and can source 2.5A and sink 5A. Since LDO provides power to the internal analog circuitry, use an RC filter from LDO to DLOV as shown in Figure 1 to minimize noise at LDO. LDO also supplies the 4.096V reference (REF) and most of the internal control circuitry. Bypass LDO with a 1F or greater capacitor to GND.
Applications Information
Component Selection
Table 4 lists the recommended components and refers to the circuit of Figure 1. The following sections describe how to select these components.
MOSFETs
The MAX1870A requires one p-channel MOSFET and one n-channel MOSFET. Component substitutions are permissible as long as the on-resistance and gate charge are equal or lower and the voltage, current, and power-dissipation ratings are high enough. If using a lower-power application, scale down the MOSFETs with lower gate charge and the MOSFET's on-resistance can be scaled up. For example, in a system designed to deliver half as much current, MOSFETs selected with twice the on-resistance and half as much gate charge ensure equal or better efficiency, and reduce size and cost. If resistive losses dominate, it can be possible to reduce the gate charge at the cost of on-resistance and still achieve a similar efficiency. Make sure that the linear regulators can drive the selected MOSFETs. The average current required to drive a given MOSFET is: ILDO = QgM2 x fswitch IVHN = QgM1 x fswitch where fswitch is 400kHz (typ).
CSSP CLS CSS ACSS RS1_ CSSN/ CSSS GMS
CCS CCS
GMPWM
ROGMS
Figure 12. CCS Simplified Loop Diagram
CCI LOOP RESPONSE
100 80 60 MAGNITUDE (dB) 40 -45 20 0 PHASE -20 -40 0.1 10 1k FREQUENCY (Hz) 100k -90 -20 -40 0.1 MAG 0 100 80 60 MAGNITUDE (dB) 40 20 0
CCS LOOP RESPONSE
0
MAG -45
PHASE
-90 10 1k FREQUENCY (Hz) 100k 10M
Figure 13. CCI and CCS Loop Response
26
______________________________________________________________________________________
Step-Up/Step-Down Li+ Battery Charger
MOSFET Power Dissipation
Table 5 shows the resistive losses and switching losses in each of the MOSFETs during either step-up or stepdown operation. Table 5 provides a first-order estimate, but does not consider second-order effects such as ripple current or nonlinear gate drive. For typical applications where VBATT / 2 < VIN < 2 x VBATT, the resistive losses are primarily dissipated in M1 since M2 operates at a lower duty cycle. Switching losses are dissipated in M1 when in step-down mode and in M2 when in step-up mode. Ratio the MOSFETs so that resistive losses roughly equal switching losses when at maximum load and typical input/output conditions. The resistive loss equations are a good approximation in hybrid mode (VIN near VBATT). Both M1 and M2 switching losses apply in hybrid mode. Switching losses can become a heat problem when the maximum AC adapter voltage is applied in step-down operation or minimum AC adapter voltage is applied with a maximum battery voltage. This behavior occurs because of the squared term in the CV2 f switching-loss equation. Table 5 provides only an estimate and is not a substitute for breadboard evaluation. hybrid mode, select LIR for operating in this mode. Select the inductance according to the following equation: L= 2 x VIN x t min LIR ICHG
MAX1870A
Larger inductance values can be used; however, they contribute extra resistance that can reduce efficiency. Smaller inductance values increase RMS currents and can also reduce efficiency. Saturation Current Rating The inductor must have a saturation current rating high enough so it does not saturate at full charge, maximum output voltage, and minimum input voltage. In step-up operation, the inductor carries a higher current than in step-down operation with the same load. Calculate the inductor saturation current rating by the following equation: ISAT VOUT_ MAX x ICHG_ MAX + VIN _MIN VIN _MIN T x VIN _ MIN x 1 - VOUT_MAX 2xL
Inductor Selection
Select the inductor to minimize power dissipation in the MOSFETs, inductor, and sense resistors. To optimize resistive losses and RMS inductor current, set the LIR (inductor current ripple) to 0.3. Because the maximum resistive power loss occurs at the step-up boundary of
Input-Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OS-
Table 4. Component List
DESIGNATION INDUCTORS Sumida CDRH104R-100 Sumida CDRH104R-7R0 Sumida CDRH104R-5R2 Sumida CDRH104R-3R8 10H, 4.4A, 35m power inductor 7H, 4.8A, 27m power inductor 5.2H, 5.5A, 22m power inductor 3.8H, 6A, 13m power inductor PART NUMBER SPECIFICATIONS
L1
P-CHANNEL MOSFETs Siliconix Si4435DY Fairchild FDC602P Fairchild FDS4435A Fairchild FDW256P P-FET 35m, QG = 17nC, VDSMAX = 30V, 8-pin SO P-FET 35m, QG = 14nC, VDSMAX = 20V, 6-pin SuperSOT P-FET 25m, QG = 21nC, VDSMAX = 30V, 8-pin SO P-FET 20m, QG = 28nC, VDSMAX = 30V, 8-pin TSSOP
M1
N/P-CHANNEL MOSFET PAIRS M1/M2 Fairchild FDW2520C (8-pin TSSOP) N-FET 18m, QG = 14nC, VDSMAX = 20V, P-FET 35m, QG = 14nC, VDSMAX = 20V N-FET, 9m, QG = 18nC, VDSMAX = 30V, 8-pin SO
N-CHANNEL MOSFETs M2 IRF7811W
______________________________________________________________________________________
27
Step-Up/Step-Down Li+ Battery Charger MAX1870A
Table 5. MOSFET Resistive and Switching Losses
DESIGNATION STEP-DOWN MODE DC LOSSES STEP-UP MODE
M1
VBATT x ICHG2 x RDS(ON) VDCIN VBATT 1 - x ICHG VDiode VDCIN
VBATT 2 x ICHG x RDS(ON) VDCIN
D4
0
M2 D3
0 ICHG x VDIODE
VDCIN VBATT 2 x ICHG x RDS(ON) 1 - x VBATT VDCIN
ICHG x VDIODE SWITCHING LOSSES
M1 D4 M2 D3
VDCIN(MAX)2 x CLX x fSW ICHG IGATE
0 0 0
0 0
VBATT(MAX)3
x CLX x fSW ICHG IGATE x VDCIN(MAX)
0
Note: CLX is the total parasitic capacitance at the drain terminals of M1 and M2. IGATE is the peak gate-drive source/sink current of M1 or M2.
CON) are preferred due to their resilience to power-up surge currents. The input capacitors should be sized so that the temperature rise due to ripple current in continuous conduction does not exceed approximately 10C. Choose a capacitor with a ripple current rating higher than 0.5 x ICHG.
Battery-Removal Response
Upon battery removal, the MAX1870A continues to regulate a constant inductor current until the battery voltage, V BATT , exceeds the regulation threshold. The MAX1870A's response time depends on the bandwidth of the CCV loop, f CO (see the Voltage Loop Compensation section). For applications where battery overshoot is critical, either increase COUT or increase f CO by increasing R CV . See Battery Insertion and Removal in the Typical Operating Characteristics.
Output-Capacitor Selection
The output capacitor absorbs the inductor ripple current in step-down mode, or a peak-to-peak ripple current equal to the inductor current when in step-up or hybrid mode. As such, both capacitance and ESR are important parameters in specifying the output capacitor. The actual amplitude of the ripple is the combination of the two. Ceramic devices are preferable because of their resilience to surge currents. The worst-case output ripple occurs during hybrid mode when the input voltage is at its minimum. See the Typical Operating Characteristics. Select a capacitor that can handle 0.5 x ICHG x VBATT / VIN while keeping the rise in capacitor temperature less than 10C. Also, select the output capacitor to tolerate the surge current delivered from the battery when it is initially plugged into the charger.
System Load Transient
The MAX1870A battery charger features a very fast response time to system load transients. Since the input current loop is configured as a single-pole system, the MAX1870A responds quickly to system load transients (see the System Load-Transient Response graph in the Typical Operating Characteristics). This reduces the risk of tripping the overcurrent threshold of the wall adapter and minimizes requirements for adapter oversizing.
28
______________________________________________________________________________________
Step-Up/Step-Down Li+ Battery Charger
Layout And Bypassing
Bypass DCIN with a 1F to ground (Figure 1). Optional diodes D1 and D2 protect the MAX1870A when the DC power-source input is reversed. A signal diode for D1 is adequate because DCIN only powers the LDO and the internal reference. Good PC board layout is required to achieve specified noise, efficiency, and stable performance. The PC board layout artist must be given explicit instructions--preferably, a pencil sketch showing the placement of the power-switching components and high-current routing. Refer to the PC board layout in the MAX1870A evaluation kit for examples. A ground plane is essential for optimum performance. In most applications, the circuit is located on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current connections (PGND, DHI, VHP, VHN, BLKP, and DLOV), the bottom layer for quiet connections (CSSP, CSSN, CSSS, CSIP, CSIN, REF, CCV, CCI, CCS, DCIN, LDO and GND), and the inner layers for an uninterrupted ground plane. Use the following step-by-step guide: 1) Place the high-power connections first, with their grounds adjacent: * Minimize the current-sense resistor trace lengths, and ensure accurate current sensing with Kelvin connections. Use independent branches for CSSP, CSSS, CSSN, CSIP, and CSIN. * Minimize ground trace lengths in the high-current paths. * Minimize other trace lengths in the high-current paths. * Use >5mm wide traces for high-current paths. Ideally, surface-mount power components are flush against one another with their ground terminals almost touching. These high-current grounds are then connected to each other with a wide, filled zone of top-layer copper, so they do not go through vias. Other high-current paths should also be minimized, but focus primarily on short ground and current-sense connections to eliminate about 90% of all PC board layout problems. 2) Place the IC and signal components. Keep the main switching nodes (inductor connectons) away from sensitive analog components (current-sense traces and REF capacitor). Important: the IC must be no further than 10mm from the current-sense resistors. Keep the gate-drive traces (DHI and DBST) shorter than 20mm, and route them away from the current-sense lines and REF. Place ceramic bypass capacitors close to the IC. The bulk capacitors can be placed further away. Bypass CSSP, CSSN, CSIN, and CSIP to analog GND to reduce switching noise and maintain input-current and charger-current accuracy. Place the current-sense input filter capacitors under the part, connected directly to GND. 3) Use a single-point star ground placed directly below the part. Connect the input ground trace, power ground (subground plane), and normal ground to this node. Figure 14 shows a partial layout of the power path and components. Refer to the EV kit data sheet for more information.
MAX1870A
______________________________________________________________________________________
29
Step-Up/Step-Down Li+ Battery Charger MAX1870A
BATT
C9
PGND
M2
N
P
M1
Figure 14. Recommended Layout for the MAX1870A
Pin Configuration
CSSN CSSP CSSS VHN VHP DHI DLOV DCIN
RS2 L1 D3 D4 C8
IN
RS1b
LOAD
TOP VIEW
TRANSISTOR COUNT: 6484 PROCESS: BiCMOS
RS1a
Chip Information
32
31
30
29
28
27
26
25
LDO REF CLS GND CCV CCI CCS GND
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22 21
I.C. PGND DBST I.C. I.C. BLKP CSIP CSIN
MAX1870A
20 19 18 17
REFIN
VCTL
ASNS
ICTL
CELLS
SHDN
IINP
THIN QFN
30
______________________________________________________________________________________
BATT
Step-Up/Step-Down Li+ Battery Charger
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS
MAX1870A
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1
A3
PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
21-0140
E
1
2
______________________________________________________________________________________
31
Step-Up/Step-Down Li+ Battery Charger MAX1870A
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T2055-2 T2055-3 T2055-4 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T3255-2 T3255-3 T3255-4 T4055-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20
NOM. MAX. ALLOWED
DOWN BONDS
3.00 3.00 3.00 3.00 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 3.20
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.40 BSC. 0.25 - 0.25 - 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 0.30 0.40 0.50 40 10 10 -
NO YES NO YES NO NO NO YES YES NO NO YES NO YES NO YES
3.30 3.40 3.20
3.30 3.40
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
21-0140
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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